Last Updated: 05.10.2008
Mihai's Web Pages
1998-2000. M.Phil (Master of Philosophy) in Electrical Engineering, University of Sheffield, UK, Department of Electronic and Electrical Engineering.
M.Phil dissertation: Low Power Design of Integrated Circuits
1990-1995. Diploma of Engineering (M.Eng.), Transilvania University Brasov, Romania, Faculty of Electrical Engineering, Dept. of Electronics and Computers. Graduated with 91.80%
Final year project dissertation: Method for Vectorisation of the Musical Instruments Sound, with Multimedia Application
1986-1990 Andrei Saguna National College Brasov, Mathematics and Physics field, graduated with 81.50%.
September 2008 - . VLSI engineer Tessera, Fotonation group, Brasov, Romania
July 2007 - August 2008. Application Engineer, eASIC, Brasov, Romania
As part of the Application Engineering team I was responsible of assisting eASIC customers in successfully implementing their designs on eASIC's Nextreme structured ASIC technology- from RTL to tape-out
April 2001 - June 2007. Senior Development Engineer, NXP Semiconductors (Philips Semiconductors until 2007), Zurich, Switzerland, BL Mobile Communications, MST Base-band, Digital Designs Group.
The Base-band group is developing multimedia base-band chips for 2.5G to 3.5G mobile phones. These are complex multi-core system on chip ICs, developed in a multi-site environment. The IC design, firmware and software teams are spread world-wide (Zurich, Sophia Antipolis, Shanghai, Nurenberg, Caen, Le Mans and others).
Over time, my main responsibilities covered a wide spectrum of activities, from RTL design and IP integration to software development for IC validation and verification and from tools/platforms evaluation to CAD flow development:
System on Chip Prototyping on FPGA.
Leader of the prototyping activities: complete FPGA mapping flow of entire base-band chips
Coordination between the hardware design team and the validation and firmware teams
Permanent contact with R&D and support engineers from various CAD and prototyping systems vendors
FPGA platform integration with Hardware Emulators (Cadence Quickturn)
Specification and design review of various adapter boards needed for FPGA validation
IC Validation
Responsible for the validation of the camera interface of one base-band chip
Development of software drivers and validation application in C
IC Verification
Working with component based software and hardware abstraction layer
Verification of various IPs of our designs, including the DSP subsystem
RTL Design and Integration of several digital IPs into our chip designs
Digital Circuit Synthesis of various IPs for silicon implementation and complex systems on FPGA
Supervising trainees on several topics:
SystemC evaluation and integration into the test bench environment
FPGA mapping and maintenance of complex System on Chip projects
Formal Verification of circuits
Lab Experience - set-up, debug (SW debugger, logic analyser etc.), IC evaluation
Rich working experience with release based complex design databases under revision control systems
Training sessions: Deep Sub-micron IC Design, Expert VHDL, SystemC, ARM, Verification Software, DfT Basics, Circuit Synthesis, Project Leading, CMMI (Capability Maturity Model® Integration) Introduction
March 1998 - Dec. 2000. Research Assistant, University of Sheffield, UK, Department of Electronic and Electrical Engineering, Electronic Systems Design Group
My work was part of the PREST (Power Reduction for System Technology) project, funded by the Commission of the European Community. Three Universities from UK and one company (Mitel) were involved in this project. Each party designed a Viterbi Processor Chip with the same pad ring and interface but different cores, using different low power techniques at architecture and circuit level. All four chips were produced and evaluated.
My responsibilities in this project were:
Literature survey in the field of low power circuit design
Development of a complete low power SPL cell library using 0.35um, 3.3V and 0.18um, 1.8V CMOS technology
Development of a circuit synthesis Java tool for SPL circuits. The tool is based on BDD (Binary Decision Diagrams). It is still maintained under GPL: BeDD
Design of an SPL low power Viterbi Decoder arithmetic core (Viterbi Trellis with Add-Compare-Select blocks) for DVB (Digital Video Broadcast) and DSS (Digital Satellite Systems), using the 0.35um SPL cell library
Integration of the SPL arithmetic core with the rest of the Viterbi chip, which was designed using standard CMOS logic
The Viterbi chip has been fabricated and later tested by my colleagues (after the end of my contract). It meets and exceeds the specifications and consumes about 2.5x less power than the original chip built with standard CMOS logic cells in the same technology
Oct. 1996 - March 1998. System engineer, Mediapro International, Radio ProFM Brasov Romania.
Studio design and installation. I was the very first employee of the new radio studio
Studio and broadcasting equipment maintenance
Web site design and maintenance
June 1996 - Oct. 1996. Deuroconsult S.R.L., Brasov, Romania
Computer graphics and web design
Aug. 1995 - May 1996. Tunele S.A. Building Enterprise, Brasov, Romania
Computer engineer at Dept. of Computing Systems
1998. Java programming, remote collaboration for Terra Firma Design, Fort Collins, Colorado, US
1996-98. Web design, remote collaboration for Open Books System, Rockport, Massachusetts, US
May and October 1995, trainee student at Sincrotrone Research Center, Trieste, Italy, Special Instrumentation Laboratory. Design and test of two dedicated FPGA integrated circuits
IC Development: RTL coding in VHDL and Verilog; Simulation: ncsim, Modelsim; Synthesis: Synplicity, Magma, ISE, Cadence Ambit; Formal verification: Conformal; Static Timing Analysis: Primetime, Synplicity; Analog Flow: IC Layout Design (Virtuoso), DRC, Extract, ERC, LVS, Spice
Programming languages: VHDL, Verilog, Perl, C, C++, make, Java, SystemC, Assemblers, BeanShell, Java Script, TCL, Matlab, html, css, Doxygen
Good understanding of version control and release based methodologies. I worked with Synchronicity DesignSync, CVS, SOS
Embedded software development and debugging for ARM processors and REAL DSPs. Familiar with the ARM Lauterbach Debugger; FPGA debug: probes, ChipScope
Image/Photo editing (Photoshop, Imagemagick, Gimp) and sound processing
Familiar with many operating systems: Unix (Linux, Max OS X, HP-UX, Solaris), windows
English: fluent writing and speaking
Romanian: mother tongue
German: very basic
Markus Wannemacher, Mihai Munteanu, Sacha Perret, Rolf Singer, Philips Semiconductors. Taking the Best Out of Two Worlds: Prototyping and Hardware Emulation, Seventh Annual IEEE International Workshop on High Level Design Validation and Test Cannes, France, October 27-29, 2002
M. Munteanu, P.A. Ivey, L. Seed, M. Psilogeorgopoulos, N. Powell, I. Bogdan. Single Ended Pass-Transistor Logic - A comparison with CMOS and CPL. VLSI '99 - Lisbon, Portugal, December 1 - 4, 1999. In: VLSI: Systems on a Chip, Kluwer Academic Publishers, 1999, pp. 206-217, ISBN 0-7923-7731-1
M. Munteanu, I. Bogdan, P.A. Ivey, N. Powell, M. Psilogeorgopoulos, L. Seed, T.S. Chuang. Single Ended Pass-Transistor Logic for Low Power Design. Proceedings of the 33rd Asilomar Conference on Signals, Systems and Computers, Monterey, California, USA, October 1999, pp. 364-368
I. Bogdan, M. Munteanu, P.A. Ivey, N.L. Seed, N. Powell Power Reduction Techniques for a Viterbi Decoder Implementation. ESPLD 2000 (European Low Power Initiative for Electronic System Design) Third International Workshop July 25-28 2000 - Rapallo, Italy, ISBN 90-5326-036-6, pp 28-48
Mihai Munteanu. SPL Synthesis using BDDs. Poster presented at the Como Low Power Conference 1999
Design of the year - Philips Semiconductors 2004. Our IC development team won this very important yearly Philips Semiconductors award with our state of the art multimedia 2.5G base-band chip for mobile communications
Download of the Week award at JavaBoutique.internet.com for Menu Applet Java Applet in Feb. 2000
Special prize in the Dept. of Electronics and Computers Engineering Scientific Communication Session, Brasov - Romania 1995, for A Method for Vectorisation of the Musical Instruments Sound, with Multimedia Application
Prize in the Transilvania University Scientific Communication Session, (Geometry and Technical Drawing section) for Original 3D Puzzles, Brasov - Romania 1991
Outdoor Sports: ski (ski instructor: 1991-1994), ski touring, hiking, mountain bike
Digital Photography, Web publishing
Music; playing blues harmonica. Romanian Jazz and Folk National Festivals participations and awards. Third place at Harmonica Contest (blues section) of the National Harmonica League of Great Britain 14, Nov. 1998
Available upon request